香山是一款开源的高性能 RISC-V 处理器,基于 Chisel 硬件设计语言实现,支持 RV64GC 指令集。

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.github 8cf339f1fa ci: add `gcpt-restore-bin` arg for all gcpt workload 4 days ago
coupledL2 @ fd53c7ba69 70eea123e7 fanout: change entry reset into async-reset (#3229) 1 day ago
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difftest @ 503f829ea8 42d59059dc bump difftest (#3255) 1 day ago
fudian @ e1bd4695ca 45f43e6e5f chore: bump chisel 6.0.0 (#2654) 6 months ago
huancun @ f9dffb2dd4 bb2f3f51dd perf: use perfUtils in `Utility` (#3190) 1 week ago
images 7a2fc509e2 misc: fix typo in nanhu arch figure (#1552) 2 years ago
macros 01cdded872 NewCSR: fix unprivileged CSRs and permission check 4 days ago
openLLC @ 9973f00309 bb2f3f51dd perf: use perfUtils in `Utility` (#3190) 1 week ago
project 5a7b942b03 update sbt version 5 years ago
ready-to-run @ 7e6f25836c 84b3098230 NewCSR: support trigger csr in difftest (#3232) 1 day ago
rocket-chip @ e64b744b14 195ef4a53a build: bump chisel 3.6.1, scala 2.13.14, mill 0.11.8, etc. (#3118) 3 weeks ago
scripts bc247239b2 script: add `gcpt-restore-bin` arg to specify the gcpt restore bin 4 days ago
src 7a63335a24 MissUnit: update replacer only when acuqire fire (#3245) 17 hours ago
tools f320e0f01b misc: update PCL information (#899) 3 years ago
utility @ de50694f6f bb2f3f51dd perf: use perfUtils in `Utility` (#3190) 1 week ago
yunsuan @ c9ddad04af ae0295f432 chore: bump chisel 6.5.0 (#3210) 4 days ago
.gitignore aee6a6d1b2 l2bop: train by virtual address and buffer tlb req (#2382) 2 months ago
.gitmodules 720dd6218e top: implement XSNoCTop and standalone devices (#3136) 2 weeks ago
.mill-version 195ef4a53a build: bump chisel 3.6.1, scala 2.13.14, mill 0.11.8, etc. (#3118) 3 weeks ago
LICENSE c6d439803a Add MulanPSL-2.0 License (#824) 3 years ago
Makefile 720dd6218e top: implement XSNoCTop and standalone devices (#3136) 2 weeks ago
Makefile.test 51981c77c3 test: add example of chiseltest's unit-test and generating verilog for xs' module (#1890) 1 year ago
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readme.zh-cn.md 5931ace353 refactor directory hierarchy for two chisel versions (#2423) 8 months ago
scalastyle-config.xml 945710d1cb first commit 5 years ago
scalastyle-test-config.xml 945710d1cb first commit 5 years ago

README.md

XiangShan

XiangShan (香山) is an open-source high-performance RISC-V processor project.

中文说明在此

Copyright 2020-2022 by Institute of Computing Technology, Chinese Academy of Sciences.

Copyright 2020-2022 by Peng Cheng Laboratory.

Docs and slides

XiangShan-doc is our official documentation repository. It contains design spec., technical slides, tutorial and more.

Publications

MICRO 2022: Towards Developing High Performance RISC-V Processors Using Agile Methodology

Our paper introduces XiangShan and the practice of agile development methodology on high performance RISC-V processors. It covers some representative tools we have developed and used to accelerate the chip development process, including design, functional verification, debugging, performance validation, etc. This paper is awarded all three available badges for artifact evaluation (Available, Functional, and Reproduced).

Artifacts Available Results Reproduced

Paper PDF | IEEE Xplore | BibTeX | Presentation Slides | Presentation Video

Follow us

Wechat/微信:香山开源处理器

Zhihu/知乎:香山开源处理器

Weibo/微博:香山开源处理器

You can contact us through our mail list. All mails from this list will be archived to here.

Architecture

The first stable micro-architecture of XiangShan is called Yanqihu (雁栖湖) on the yanqihu branch, which has been developed since June 2020.

The second stable micro-architecture of XiangShan is called Nanhu (南湖) on the nanhu branch.

The current version of XiangShan, also known as Kunminghu (昆明湖), is still under development on the master branch.

The micro-architecture overview of Nanhu (南湖) is shown below.

xs-arch-nanhu

Sub-directories Overview

Some of the key directories are shown below.

.
├── src
│   └── main/scala         # design files
│       ├── device         # virtual device for simulation
│       ├── system         # SoC wrapper
│       ├── top            # top module
│       ├── utils          # utilization code
│       └── xiangshan      # main design code
│           └── transforms # some useful firrtl transforms
├── scripts                # scripts for agile development
├── fudian                 # floating unit submodule of XiangShan
├── huancun                # L2/L3 cache submodule of XiangShan
├── difftest               # difftest co-simulation framework
└── ready-to-run           # pre-built simulation images

IDE Support

bsp

make bsp

IDEA

make idea

Generate Verilog

  • Run make verilog to generate verilog code. The output file is build/XSTop.v.
  • Refer to Makefile for more information.

Run Programs by Simulation

Prepare environment

  • Set environment variable NEMU_HOME to the absolute path of the NEMU project.
  • Set environment variable NOOP_HOME to the absolute path of the XiangShan project.
  • Set environment variable AM_HOME to the absolute path of the AM project.
  • Install mill. Refer to the Manual section in this guide.
  • Clone this project and run make init to initialize submodules.

Run with simulator

  • Install Verilator, the open-source Verilog simulator.
  • Run make emu to build the C++ simulator ./build/emu with Verilator.
  • Refer to ./build/emu --help for run-time arguments of the simulator.
  • Refer to Makefile and verilator.mk for more information.

Example:

make emu CONFIG=MinimalConfig EMU_THREADS=2 -j10
./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so

Troubleshooting Guide

Troubleshooting Guide