香山是一款开源的高性能 RISC-V 处理器,基于 Chisel 硬件设计语言实现,支持 RV64GC 指令集。
Xuan Hu 257429298d fix(Ebreak): use isPcBkpt to hold exception raised by ebreak (#3769) | 1 天之前 | |
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.github | c08f49a0db fix(Trigger): remove tcontrol in trigger module. | 2 周之前 |
coupledL2 @ f1de8dac4f | c3d1dc24af submodule(CoupledL2): bump CoupledL2 (#3764) | 3 天之前 |
debug | 214933efeb bump difftest & mkdir for wave/perf for local-ci script's run-mode (#1927) | 1 年之前 |
difftest @ e3cd34c349 | 7c0bbe3b65 submodule(difftest): bump difftest to remove `tcontrol`. | 2 周之前 |
fudian @ e1bd4695ca | 45f43e6e5f chore: bump chisel 6.0.0 (#2654) | 9 月之前 |
huancun @ 3fc7e7e0c2 | e1d5ffc2d9 submodule(CoupledL2, HuanCun): bump (#3487) | 1 月之前 |
images | 7a2fc509e2 misc: fix typo in nanhu arch figure (#1552) | 2 年之前 |
macros | 01cdded872 NewCSR: fix unprivileged CSRs and permission check | 3 月之前 |
openLLC @ 0bf0448309 | 3ea4388c30 RVA23: Support Sv48 & Sv48x4 (#3406) | 2 月之前 |
project | 5a7b942b03 update sbt version | 5 年之前 |
ready-to-run @ c9c1451937 | 78f118b099 submodule(ready-to-run): bump nemu ref (#3767) | 3 天之前 |
rocket-chip @ 2c117a41bb | 1bc48dd1fa fix(Zcb): fix illegal instruction condition of zcb instructions (#3680) | 2 周之前 |
scripts | e76e9e542a ci(enable-fork): set fork interval to 10 seconds (#3694) | 3 天之前 |
src | 257429298d fix(Ebreak): use isPcBkpt to hold exception raised by ebreak (#3769) | 1 天之前 |
tools | f320e0f01b misc: update PCL information (#899) | 3 年之前 |
utility @ 051d07961c | 4446722468 fix(csr): intermediate data should be stored when output not fire (#3634) | 3 周之前 |
yunsuan @ f568aa0156 | 0e43419882 submodule(YunSuan): bump yunsuan to fix neg of condition for f32toi16 (#3494) | 1 月之前 |
.gitignore | aee6a6d1b2 l2bop: train by virtual address and buffer tlb req (#2382) | 5 月之前 |
.gitmodules | 720dd6218e top: implement XSNoCTop and standalone devices (#3136) | 3 月之前 |
.mill-version | 195ef4a53a build: bump chisel 3.6.1, scala 2.13.14, mill 0.11.8, etc. (#3118) | 3 月之前 |
LICENSE | c6d439803a Add MulanPSL-2.0 License (#824) | 3 年之前 |
Makefile | bbb9b7beb5 fix(combmem): remove x assignment if ren is low (#3667) | 3 周之前 |
Makefile.test | 51981c77c3 test: add example of chiseltest's unit-test and generating verilog for xs' module (#1890) | 1 年之前 |
README.md | ab01228680 Update README.md (#3383) | 2 月之前 |
build.sbt | 5e414fe2a1 Add sbt build support (#857) | 3 年之前 |
build.sc | 26f0fb0db8 build: Force to use "en" locale when generating version timestamp (#3376) | 2 月之前 |
readme.zh-cn.md | 5931ace353 refactor directory hierarchy for two chisel versions (#2423) | 1 年之前 |
scalastyle-config.xml | 945710d1cb first commit | 5 年之前 |
scalastyle-test-config.xml | 945710d1cb first commit | 5 年之前 |
XiangShan (香山) is an open-source high-performance RISC-V processor project.
中文说明在此。
Copyright 2020-2022 by Institute of Computing Technology, Chinese Academy of Sciences.
Copyright 2020-2022 by Peng Cheng Laboratory.
XiangShan-doc is our official documentation repository. It contains design spec., technical slides, tutorial and more.
Our paper introduces XiangShan and the practice of agile development methodology on high performance RISC-V processors. It covers some representative tools we have developed and used to accelerate the chip development process, including design, functional verification, debugging, performance validation, etc. This paper is awarded all three available badges for artifact evaluation (Available, Functional, and Reproduced).
Paper PDF | IEEE Xplore | BibTeX | Presentation Slides | Presentation Video
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You can contact us through our mail list. All mails from this list will be archived to here.
The first stable micro-architecture of XiangShan is called Yanqihu (雁栖湖) on the yanqihu branch, which has been developed since June 2020.
The second stable micro-architecture of XiangShan is called Nanhu (南湖) on the nanhu branch.
The current version of XiangShan, also known as Kunminghu (昆明湖), is still under development on the master branch.
The micro-architecture overview of Nanhu (南湖) is shown below.
Some of the key directories are shown below.
.
├── src
│ └── main/scala # design files
│ ├── device # virtual device for simulation
│ ├── system # SoC wrapper
│ ├── top # top module
│ ├── utils # utilization code
│ └── xiangshan # main design code
│ └── transforms # some useful firrtl transforms
├── scripts # scripts for agile development
├── fudian # floating unit submodule of XiangShan
├── huancun # L2/L3 cache submodule of XiangShan
├── difftest # difftest co-simulation framework
└── ready-to-run # pre-built simulation images
make bsp
make idea
make verilog
to generate verilog code. The output file is build/XSTop.v
.Makefile
for more information.NEMU_HOME
to the absolute path of the NEMU project.NOOP_HOME
to the absolute path of the XiangShan project.AM_HOME
to the absolute path of the AM project.mill
. Refer to the Manual section in this guide.make init
to initialize submodules.make emu
to build the C++ simulator ./build/emu
with Verilator../build/emu --help
for run-time arguments of the simulator.Makefile
and verilator.mk
for more information.Example:
make emu CONFIG=MinimalConfig EMU_THREADS=2 -j10
./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so