代码
注册 登录
简体中文
简体中文 English
openoker
/
XiangShan
1
0
收藏 0
文件 工单管理 0 Wiki
分支: master
分支列表 标签列表

提交历史

作者 SHA1 备注 提交日期
  Xuan Hu 257429298d fix(Ebreak): use isPcBkpt to hold exception raised by ebreak (#3769) 1 天之前
  Tang Haojin 78f118b099 submodule(ready-to-run): bump nemu ref (#3767) 3 天之前
  Xuan Hu ddb4906285 fix(VecExcp): commit vls exception after Rab commiting all reg pairs 3 天之前
  Anzooooo b998549809 fix(StoreQueue): fix the assert condition when `databuffer` enqueue. 3 天之前
  Tang Haojin e76e9e542a ci(enable-fork): set fork interval to 10 seconds (#3694) 3 天之前
  happy-lx 4c5e04f234 fix(misalign): fix misaligned HLV and HLVX (#3759) 3 天之前
  Haoyuan Feng c3d1dc24af submodule(CoupledL2): bump CoupledL2 (#3764) 3 天之前
  Anzooooo a8db6d30bf fix(StoreQueue): The vecExceptionFlag can only be raised when the `databuffer.fire` 5 天之前
  xiaofeibao 3bba894fe1 fix(Backend): add vecLoadFinalIssueResp 5 天之前
  Xuan Hu 8ab9d9d04c fix(Rab): no need to limit diff commit valid only assert in commit state (#3760) 3 天之前
  Xuan Hu fe52823c75 fix(Breakpoint): memory trigger set {m|s|vs}tval with faulting address (#3762) 4 天之前
  happy-lx 5abd6e416a fix(misalign): Dont mark misalign store as commit (#3758) 5 天之前
  Xuan Hu 36c15e45ac fix(VecExcp): only one vreg need merge when vlNreX inst raise exception (#3736) 5 天之前
  Anzo bfeba862da fix(MemBlock): more accurate vector ready signal (#3741) 5 天之前
  Jiru Sun 70f6b69f5c timing(HPM): pass Coupled L2 HPM signal through memblock (#3747) 5 天之前
  Xuan Hu 11bd888f88 fix(VecExcp): use `isEnqExcp` to distinguish pc and mem trigger (#3755) 5 天之前
  Guanghui Cheng b501491c87 fix(Step): It shouldn't be a uop stepped but a machine instruction (#3746) 5 天之前
  Tang Haojin af3eaba07c timing(IMSIC): AXI4 output should be buffered (#3757) 5 天之前
  Guanghui Cheng 064c9c5a65 fix(wfi): WFI should be treated as `nop` when stepped or in dmode (#3715) 6 天之前
  Guanghui Cheng f634b231d2 fix(rob): VstartEn should be asserted when triggerAction is debug (#3745) 6 天之前
  Zhaoyang You 8c0eee90da fix(csr): Delay trap of hvictl inject passed to difftest until VecExcpMod not busy (#3744) 6 天之前
  Haoyuan Feng fab8b27428 fix(SimTop): Set sim memory size same as PMA (#3750) 6 天之前
  happy-lx eb5aa89c9a fix(misalign): enter storeMisalignBuffer when tlb hit (#3742) 6 天之前
  happy-lx 21f3709a09 fix(misalign): fix wrong gpa in misalignBuffer (#3739) 6 天之前
  Anzo cbbad3d982 fix(VMergeBuffer): vl of fof only allows setting smaller values (#3733) 6 天之前
  Xuan Hu 93f531d550 submodule(ready-to-run): bump nemu ref (#3740) 6 天之前
  Ding Haonan bfc5d9a2d7 submodule(CoupledL2): fix bug in TX buffer under DCT (#3738) 6 天之前
  happy-lx fe3c789c99 fix(csr): fix width of instruction commit (#3734) 1 周之前
  sinsanction bd3e32c124 fix(Backend, Mem): add `isFromLoadUnit` to avoid other units polluting RegCache (#3731) 1 周之前
  unlsycn d8c6b93155 docs(rob): remove outdated comments about interrupt_safe (#3729) 1 周之前

更新的提交 更旧的提交