STA RS
16 * 2

AGU
ST

AGU
ST

ALU

ALU

ALU

MDU

ALU RS
16 * 2

ALU

AGU
LD

AGU
LD

MDU RS
16 *2

MDU

MISC
16

MISC

* 128 4K-page entries, 8 4K-page/superpage entries

FMAC RS
16 * 2

FMISC RS
16 * 2

FMAC

FMAC

FMAC

FMAC

FMISC

FMISC

Rename & Dispatch

Frontend

Float Block

Integer Block

Memory Block

STD RS
16 * 2

LD RS
16 * 2

8 Bytes

2 cachelines
(2 x 64 Bytes)

predict result

32 Bytes

6 Instrs

6 Uops

FTQ Req

redirect / update

Scheduler

Backend
Redirect / Update

PC read result for Backend

DTLB*

DTLB*

DTLB*

DTLB*

FMAC RS
16 * 2

ALU RS
16 * 2